1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having a semiconductor memory comprising an error checking and correcting circuit.
2. Description of the Related Art
It is important for memories with error checking and correcting (ECC) circuits to make ECC operations invisible to minimize adverse effects on write/read accesses. The ECC operation may result in a useless access. Methods for minimizing the adverse effects on write/read accesses are roughly classified into:
(1) a type of method for performing an ECC operation during a cycle that does not relate to original write/read accesses, and (2) a type of method for performing an ECC operation with its adverse effects on accesses minimized.
For example, data the number of which is larger than that of I/O data are collectively read from a memory cell array. An ECC operation is performed on these data, which are then held in a temporary storage such as a register. A write/read operation is then continuously performed. Such an operation in combination with a continuous operation in a page or burst mode is more effective. However, larger power consumption results from an ECC operation performed on data the number of which is larger than that of I/O data.
Such a method is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2005-25827.